A Junction Temperature Reduction Technique for a Microprocessor Considering Temperature Coupled Leakage Power

Leakage power is emerging as a key challenge in IC design. Since leakage power has super-linear dependency on operating temperature, it becomes imperative to consider the thermal effects while optimizing leakage power. In this paper, an inter-simulation technique which accounts for leakage power and temperature variations is present. Integrating leakage model and coupled thermal-leakage simulations, the converged temperature and power distributions are achieved. In order to flatten the on chip temperature gradient, the revised floorplan design of a microprocessor is proposed. The on-chip temperature distributions are verified with measurement results using an infrared thermography method. The analysis results show that the realistic on-chip temperature distribution is a key for a precise estimation of leakage power. In addition, an important design implication is that the leakage power optimization problem has to be considered as a synthetic task considering logic organization, circuit parameters and chip floor plan.