Title :
A novel DLL-based configurable frequency synthesizer
Author :
Wang, Min ; Wen, Zhiping ; Chen, Lei ; Zhang, Yanlong
Author_Institution :
Beijing Microelectron., Tech. Instn., Beijing
Abstract :
A novel configurable frequency synthesizer based on delay-locked-loop (DLL) is presented in this paper, with maximum multiplication factor 10 and maximum division factor 16. A SRAM is employed to store configuration data for different multiplication and division factor. Users only need to change the data stored in the embedded SRAM to obtain frequency needed. The output frequency range is from 25 MHz to 1 GHz using tsmc 0.18 mum CMOS process parameters. The locking time of the DLL core is 20 mus at 100 MHz and 120 mus at 25 MHz. The cycle-to-cycle jitter of the DLL is 60 ps.The circuit can be part of a standard digital cell library and can easily be used in field programmable gate array (FPGA).
Keywords :
CMOS digital integrated circuits; SRAM chips; UHF circuits; delay lock loops; field programmable gate arrays; frequency synthesizers; DLL-based configurable frequency synthesizer; FPGA; SRAM; delay-locked-loop; digital cell library; field programmable gate array; frequency 25 MHz to 1 GHz; maximum multiplication factor; Circuit stability; Circuit synthesis; Clocks; Delay; Field programmable gate arrays; Frequency conversion; Frequency synthesizers; Jitter; Phase locked loops; Random access memory; Configurable; Delay-Locked-Loop; Frequency Synthesizer; Phased Clock;
Conference_Titel :
Neural Networks and Signal Processing, 2008 International Conference on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4244-2310-1
Electronic_ISBN :
978-1-4244-2311-8
DOI :
10.1109/ICNNSP.2008.4590361
