Application-driven dimensioning of a Coarse-Grain Reconfigurable Array

Author

Hussain, Waqar ; Ahonen, Tapani ; Garzia, Fabio ; Nurmi, Jari

Author_Institution

Dept. of Comput. Syst., Tampere Univ. of Technol., Tampere, Finland

fYear

2011

fDate

6-9 June 2011

Firstpage

234

Lastpage

239

Abstract

In this paper, we have scaled-up a Coarse-Grain Reconfigurable Array (CGRA) in specific widths to evaluate matrix-vector multiplication and radix-4 64-point Fast Fourier Transform (FFT) algorithms. The evaluation of different CGRAs is based on complexity in application mapping, performance and area utilization. Reducing the product development time and achieving higher reliability has always been the need of industry and system integrators. The low-level designers and application developers need higher performance with minimum resources. Based on our evaluation, we propose a choice of array sizes for fulfilling the needs of both system integrators and low-level designers.

Keywords

digital arithmetic; fast Fourier transforms; logic design; matrix multiplication; multiplying circuits; reconfigurable architectures; application mapping; application-driven dimensioning; area utilization; array size; coarse-grain reconfigurable array; low-level design; matrix-vector multiplication; radix-4 64-point fast Fourier transform algorithm; Arrays; Context; Kernel; Multiplexing; Reduced instruction set computing; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Adaptive Hardware and Systems (AHS), 2011 NASA/ESA Conference on

Conference_Location

San Diego, CA

Print_ISBN

978-1-4577-0598-4

Electronic_ISBN

978-1-4577-0597-7

Type

conf

DOI

10.1109/AHS.2011.5963942

Filename

5963942