DocumentCode :
2431860
Title :
Design optimization of Coulomb blockade devices
Author :
Muller, H.-O. ; Williams, D.A. ; Mizuta, H.
Author_Institution :
Cavendish Lab., Cambridge Univ., UK
fYear :
2000
fDate :
22-25 May 2000
Firstpage :
73
Lastpage :
74
Abstract :
Coulomb blockade devices are candidates for future digital applications, particularly memories. In our contribution we evaluate the electrical characteristics of grain arrays as a function of disorder and aspect ratio by means of simulation.
Keywords :
Coulomb blockade; optimisation; quantum interference devices; semiconductor device models; Coulomb blockade devices; aspect ratio; design optimization; digital applications; disorder; electrical characteristics; grain arrays; memories; simulation; Capacitance; Design optimization; Fluctuations; Geometry; Grain size; Laboratories; Lithography; Monitoring; Shape; Temperature distribution;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computational Electronics, 2000. Book of Abstracts. IWCE Glasgow 2000. 7th International Workshop on
Conference_Location :
Glasgow, UK
Print_ISBN :
0-85261-704-6
Type :
conf
DOI :
10.1109/IWCE.2000.869929
Filename :
869929
Link To Document :
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