An efficient VLSI architecture for motion estimation using new three step search algorithm

This paper presents an efficient VLSI architecture for the implementation of Motion Estimation (ME) for real-time video processing using New Three Step Search Algorithm (NTSS). The proposed architecture employs sequential processing of pixels with a view to reduce the hardware complexity and achieve real-time speed requirement simultaneously. A novel memory addressing scheme has been proposed which optimizes the address generation logic. The architecture uses only 4% FPGA slice registers and slice LUTs which translates to an equivalent gate count of 3.5K. The proposed architecture can achieve a frequency of 350 MHz and is able to process 206 CIF frames per second. It can be included in commercial equipments like camcorders, smart-phones, tablet computers etc.