DocumentCode
2432084
Title
A 6-bit 1GS/s low-power flash ADC
Author
Lien, Yu-Chang ; Lin, Ying-Zu ; Chang, Soon-Jyh
Author_Institution
Nat. Cheng-Kung Univ., Tainan, Taiwan
fYear
2009
fDate
28-30 April 2009
Firstpage
211
Lastpage
214
Abstract
This paper proposes a low-power design guideline for high speed ADCs, and a low-power ADC with this design guideline is fabricated in a 0.13 mum CMOS process. The experimental results show that the effective number of bit (ENOB) is 5.16 at the sampling frequency of 1 GHz, and the resolution bandwidth (ERBW) is higher than 500 MHz at 700 MS/s. Due to the high input bandwidth and low power consumption, this ADC is very suitable for UWB systems.
Keywords
CMOS integrated circuits; analogue-digital conversion; low-power electronics; ultra wideband technology; CMOS process; UWB systems; effective number of bit; high speed ADC; input bandwidth; low power consumption; low-power design guideline; low-power flash ADC; resolution bandwidth; sampling frequency; Bandwidth; CMOS process; Clocks; Energy consumption; Frequency; Guidelines; Interpolation; Read only memory; Sampling methods; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
Conference_Location
Hsinchu
Print_ISBN
978-1-4244-2781-9
Electronic_ISBN
978-1-4244-2782-6
Type
conf
DOI
10.1109/VDAT.2009.5158132
Filename
5158132
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