A built-in self-repair method for RAMs in mesh-based NoCs

Author

Liu, Hsiang-Ning ; Huang, Yu-Jen ; Li, Jin-Fu

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan

fYear

2009

fDate

28-30 April 2009

Firstpage

259

Lastpage

262

Abstract

Network-on-chip is one popular interconnection infrastructure for giga-scale integrated chips. Moreover, the number of memory cores in such chips usually is very large. This paper proposes an efficient built-in self-repair (BISR) method for repairing memories in NoCs. By reusing the communication links in NoCs, the BISR scheme can repair multiple memories using one BISR circuit without incurring the problem of routing. To increase the repair efficiency, a global spare memory is designed for repairing multiple memories. Experimental results show that the proposed BISR scheme can achieve very high repair efficiency. Also, the area overhead of the BISR circuit is very low-only about 1.38% for fifteen 8Ktimes64-bit memories.

Keywords

built-in self test; integrated circuit interconnections; integrated circuit reliability; integrated memory circuits; logic testing; network routing; network-on-chip; random-access storage; RAM; built-in self-repair method; giga-scale integrated chip; global spare memory; mesh-based NoC; network-on-chip; Built-in self-test; Circuit testing; Costs; Integrated circuit interconnections; Network-on-a-chip; Random access memory; Redundancy; Registers; Routing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4244-2781-9

Electronic_ISBN

978-1-4244-2782-6

Type

conf

DOI

10.1109/VDAT.2009.5158144

Filename

5158144