Title :
A 1.55ns 0.015 mm2 64-bit quad number comparator
Author :
Kim, Minsu ; Kim, Joo-Young ; Yoo, Hoi-Jun
Author_Institution :
Dept. of EECS, KAIST, Daejeon, South Korea
Abstract :
This paper proposes a fast and small area 64-bit quad binary number comparator. Proposed bit-wise comparing logic chain (BCLC) and sequential strobes (SS) scheme enables 1.55 ns 64-bit quad binary number comparison, which is 16% improvement compared to conventional comparator. With the help of BCLC and SS scheme, the proposed quad binary number comparator consumes 0.015 mm2 in 0.18 um CMOS technology. Compared to previous works, the proposed comparator shows 9% reduction of transistor count and 13% area reduction.
Keywords :
comparators (circuits); logic circuits; 64-bit quad number comparator; bit-wise comparing logic chain; sequential strobes; time 1.55 ns; Application specific processors; CMOS logic circuits; CMOS technology; Computer aided instruction; Computer architecture; Computer vision; Digital arithmetic; Digital signal processing; Digital systems; Logic circuits;
Conference_Titel :
VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-2781-9
Electronic_ISBN :
978-1-4244-2782-6
DOI :
10.1109/VDAT.2009.5158150
