Title :
A dual-band LNA with 0.18-μm CMOS switches
Author :
Lian, Low Li ; Noh, Norlaili Mohd ; Mustaffa, Mohd Tafir ; Manaf, Asrulnizam Bin Abd ; Sidek, Othman Bin
Author_Institution :
Sch. of Electr. & Electron. Eng., Univ. Sains Malaysia, Nibong Tebal, Malaysia
Abstract :
This paper proposed the design of a switchable dual-band low-noise amplifier (LNA) using Silterra 0.18-μm CMOS technology fabrication process. The LNA utilized the single-ended type with cascode inductively source degeneration topology. This topology is best for simultaneous noise and input matching besides capable of reducing the Miller effect as well as improving on the reverse isolation performance. The switchable dual-band LNA can be tuned to center frequency of either 1.575 GHz for global positioning system (GPS) or 2.4 GHz for WLAN 802.11b standard applications. The LNA can cater frequency range of 1.33 to 2.10 GHz and 1.69 to 2.64 GHz for GPS and WLAN application, respectively. The switching of the operating frequency can be achieved by capacitor selection using MOS as switches at its input and output matching network. NMOS switches were implemented as they have lower on resistance and can provide larger gain when compared with PMOS. The selection of the switches is based on the voltage supplied to each switch. The supply voltage for the LNA is 1.8 V and the voltage required to enable the MOS switches is 3 V. Pre-layout simulation for input third-order intercept points (IIP3) are +1.62 dBm and +1.17 dBm for center frequency of 1.575 GHz and 2.4 GHz, respectively. Post layout simulation shows input reflection coefficients (S11) of -15 dB and -16 dB, reverse isolation coefficients (S12) of -56 dB and -50 dB, power gains (S21) of 10 dB and 11 dB, output reflection coefficients (S22) of -13 dB and -15 dB and noise figure (NF) of 3.2 dB and 3 dB for center frequency of 1.575 GHz and 2.4 GHz, respectively. Thus, the design is able to meet the requirements of the desired standards. The LNA consumes current of 18.5 mA at both 1.575 GHz and 2.4 GHz frequencies and therefore resulting a power consumption of 33.23 mW.
Keywords :
CMOS analogue integrated circuits; Global Positioning System; MOSFET; capacitors; integrated circuit layout; low noise amplifiers; power supply circuits; wireless LAN; CMOS switches; GPS; IIP3; LNA design; Miller effect; NMOS switches; PMOS; Silterra CMOS technology fabrication process; WLAN 802.11b standard applications; capacitor selection; cascode inductively source degeneration topology; center frequency; current 18.5 mA; frequency 1.33 GHz to 2.10 GHz; frequency 1.575 GHz; frequency 2.4 GHz; frequency range; global positioning system; input matching network; input reflection coefficients; input third-order intercept points; noise figure; operating frequency; output matching network; output reflection coefficients; post layout simulation; power 33.23 mW; power consumption; power gains; prelayout simulation; reverse isolation coefficients; reverse isolation performance; simultaneous noise; single-ended type; size 0.18 mum; supply voltage; switchable dual-band LNA; switchable dual-band low-noise amplifier design; CMOS integrated circuits; Capacitors; Impedance; MOS devices; Noise figure; Switches; Transistors; MOS switches; Switchable dual-band LNA; capacitor selection; single-ended type with cascode inductively source degeneration;
Conference_Titel :
Micro and Nanoelectronics (RSM), 2011 IEEE Regional Symposium on
Conference_Location :
Kota Kinabalu
Print_ISBN :
978-1-61284-844-0
DOI :
10.1109/RSM.2011.6088317