Shuffled serial adder: an area-latency effective serial adder

The shuffled adder, a novel serial adder with a latency proportional to log₂N, where N is the operand width, is presented. It is derived from the Kogge-Stone adder, reordering the cells to obtain a slice-based structure that allows an area-time effective serial implementation. It can be fed with parallel inputs and produce parallel outputs, differently from the digit-serial approach that results in the need for a data-formatter to convert a parallel input into digits, and to collect the digits of the output word. A standard-cell VLSI implementation for different values of N is presented: area-time performances are evaluated through circuit simulations, and compared with digit-serial adders with various digit-size, proving the attractiveness of the proposed structure.