A current signal CMOS sample-and-hold circuit

Author

Luangpol, Amata ; Petchmaneelumka, Wandee ; Kamsri, Thawatchai ; Riewruja, Vanchai

Author_Institution

King Mongkut´´s Inst. of Technol. Ladkrabang, Bangkok

fYear

2007

fDate

17-20 Oct. 2007

Firstpage

171

Lastpage

174

Abstract

This article presents a current signal sample-and-hold (S/H) circuit using 0.5 mum CMOS technology. A current minimum circuit is used to sample the input signal in place of a sampling switch used in the conventional S/H circuit. The current peak detector is used to hold the signal from the minimum circuit in the "hold" state. The proposed configuration is adopted effectively to cancel switch feedthrough error. The performances of the proposed circuit are demonstrated using the PSPICE analog simulation program. Simulation results show the sampling frequency up to 100 MHz and high accuracy.

Keywords

CMOS analogue integrated circuits; integrated circuit design; peak detectors; sample and hold circuits; CMOS technology; PSPICE analog simulation program; current minimum circuit; current peak detector; current signal CMOS sample-and-hold circuit; frequency 100 MHz; sampling switch; size 0.5 mum; switch feedthrough error; Breakdown voltage; CMOS technology; Circuit simulation; Clocks; Detectors; Frequency; Sampling methods; Switches; Switching circuits; Voltage control; current-mode; minimum circuit; peak detector; sample-and-hold;

fLanguage

English

Publisher

ieee

Conference_Titel

Control, Automation and Systems, 2007. ICCAS '07. International Conference on

Conference_Location

Seoul

Print_ISBN

978-89-950038-6-2

Electronic_ISBN

978-89-950038-6-2

Type

conf

DOI

10.1109/ICCAS.2007.4406902

Filename

4406902