A Formal Definition of Logic Topology for All-to-One Reduces in Distributed Memory Parallel Computing

All-to-one reduces are used widely in distributed memory parallel computing. The logic topologies have much effect on efficiency of reduces. The logic topology is a mechanism that determines how the messages in a distributed operation are sent. Many message passing systems only support several kinds of logic topologies which are regular. But in many applications, the optimal topologies are not regular. A formal definition is given in this paper. Maybe it can provide an approach to choosing optimal logic topologies for applications.