MARS performance evaluation with different interconnection networks

The performance of MARS with shared-bus and hierarchical multiple-bus was estimated using queuing models, which were further simplified by modeling. Not only the effects of the shared data memory accesses but also the interactions among processors were addressed in the models. Four variants of the system were simulated to analyze the performance improvement resulting from write-buffer and interleaved memory under the cache coherence protocol Phoenix. Given write-buffer for ten processors, the system utilization can be improved by 34.8%. Memory interleaving in the ten-processor case can also boost the original performance by 154.2%. In the hierarchical multiple-bus system, eight processors are grouped as a cluster and packet-switching is used to transfer data. Data consistency is achieved by keeping shared data noncacheable. An analysis of system performance sensitivity, which varies with parameters, is conducted. Based on this, several guidelines for the design of the cache coherence protocol are proposed