3D integration challenges for fine pitch back side micro-bumping on ZoneBOND™ wafers

The fabrication of small pitch micro-bumps on thinned wafers after through silicon vias (TSV) reveal and back side passivation is reported. Device wafers are bonded on temporary silicon carrier using the novel ZoneBOND^TM material. Micro-bump scaling involves a reduction of the overall solder volume. These structures are now reaching such dimensions that solder diffusion becomes problematic. One key advantage of the ZoneBOND^TM material is to enable room temperature debonding process in case of solder bumps and therefore prevent any metal diffusion or solder consumption prior to stacking. The glue compatibility with the micro-bumping module and the challenges to perform these processes on the back side of device wafers are reported in this study. The main process steps studied are the lithography and its alignment accuracy as well as the electro chemical deposition of the micro-bumps.