Design optimization of sense amplifiers using deeply-scaled FinFET devices

This paper presents the design optimization of sense amplifiers made of deeply-scaled (7nm) FinFET devices in order to improve the energy efficiency of cache memories, while robust operation of the sense amplifier under process variations is achieved. To this end, an analytical solution for deriving the minimum voltage difference that can be correctly sensed between the sense amplifier inputs, considering process variations, is presented. Device parameters and transistor sizing of the sense amplifier are then optimized in order to further increase the cache energy efficiency. The optimized sense amplifier design has 2-fold lower input voltage difference compared with the baseline counterpart, which according to the architecture-level simulations, causes 26% reduction in the total energy consumption of an L1 cache memory.