Title :
In search of the optimum test set - adaptive test methods for maximum defect coverage and lowest test cost
Author :
Madge, Robert ; Benware, Brady ; Turakhia, Ritesh ; Daasch, Robert ; Schuermyer, Chris ; Ruffler, Jens
Author_Institution :
LSI Logic Corp., Gresham, OR, USA
Abstract :
Maintaining product quality at reasonable test cost in very deep sub-micron process has become a major challenge especially due to multiple manufacturing locations with varying defect and parametric distributions. Increasing vector counts and binary search routines are now necessary for subtle defect screening. In addition, parametric tests and at-spec testing is still often necessary to ensure customer quality. Systematic defects are becoming more common and threaten to dominate the yield Pareto. Adaptive test methods are introduced in This work that demonstrate the capability of increasing or decreasing the test coverage based on the predicted or measured defect and parametric behavior of the silicon being tested. Results promise an increase in product quality at the same time a reduction in test costs.
Keywords :
Pareto analysis; cost reduction; elemental semiconductors; integrated circuit testing; quality control; silicon; Pareto analysis; Si; adaptive test methods; at-spec testing; binary search routines; maximum defect coverage; parametric distributions; parametric testing; product quality; silicon; submicron process; subtle defect screening; test cost reduction; vector counts; Circuit testing; Cost function; Delay; Integrated circuit synthesis; Integrated circuit testing; Laboratories; Large scale integration; Logic circuits; Logic design; Logic testing;
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
DOI :
10.1109/TEST.2004.1386954