DocumentCode :
2438572
Title :
Minimum testing requirements to screen temperature dependent defects
Author :
Schuermyer, C. ; Ruffler, J. ; Daasch, R. ; Madge, R.
Author_Institution :
Integrated Circuits Design & Test Lab., Portland State Univ., OR, USA
fYear :
2004
fDate :
26-28 Oct. 2004
Firstpage :
300
Lastpage :
308
Abstract :
While much progress has been made screening common defects and outliers, less emphasis has been placed on testing for performance outliers and defects across the expected operating temperature range. The subject of this paper is an analysis of the minimum testing required to screen temperature dependent outliers at wafer sort and final test. The analysis is based on data obtained from 20 wafers of a 0.18 μm skew lot and at the two temperatures 30°C and 85°C. The results demonstrate a need for defect screening at multiple temperatures and the advantage of die trace in multiple temperature testing.
Keywords :
crystal defects; integrated circuit testing; 0.18 micron; 30 degC; 85 degC; defect screening; die trace; minimum testing requirements; multiple temperature testing; temperature defendent defects; temperature dependent outliers; wafer sort; Circuit testing; Costs; Integrated circuit testing; Logic testing; Production; Propagation delay; Temperature control; Temperature dependence; Temperature distribution; Temperature sensors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
Type :
conf
DOI :
10.1109/TEST.2004.1386964
Filename :
1386964
Link To Document :
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