DocumentCode :
243867
Title :
Energy-Aware Thread Scheduling for Embedded Multi-threaded Processors: Architectural Level Design and Implementation
Author :
Wickramasinghe, Mahanama ; Hui Guo
Author_Institution :
Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia
fYear :
2014
fDate :
9-11 July 2014
Firstpage :
178
Lastpage :
183
Abstract :
Energy consumption is a critical issue in embedded systems design. One way of being energy efficient is to complete the execution as early as possible. Multi-threaded processors reduce the execution time by exploiting both the instruction level and thread level parallelism, and offer an effective solution for energy saving. With a typical multi-threaded processor design, whenever the instruction pipeline has to stall due to high latency operations, the processor execution is switched to another thread so that the computing resources are effectively utilized and the processor throughput is improved. However, traditional designs use basic scheduling schemes, such as round robin, in thread selection, which is not suitable for real time execution and is inefficient for a set of threads that have unbalanced execution durations. In this paper, we propose 1) a thread scheduling approach that extends the life span of short threads to ensure the utilization efficiency of processor resources, and 2) zero-switching-time hardware design, to achieve a minimal execution time for a set of given applications. We demonstrate through experiment the effectiveness of our design.
Keywords :
embedded systems; multi-threading; power aware computing; processor scheduling; architectural level design; architectural level implementation; computing resources; embedded multithreaded processors; embedded system design; energy consumption; energy-aware thread scheduling; execution time; instruction level parallelism; instruction pipeline; processor execution; real time execution; thread level parallelism; zero-switching-time hardware design; Delays; Hardware; Instruction sets; Pipelines; Processor scheduling; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on
Conference_Location :
Tampa, FL
Print_ISBN :
978-1-4799-3763-9
Type :
conf
DOI :
10.1109/ISVLSI.2014.55
Filename :
6903356
Link To Document :
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