DocumentCode :
2439217
Title :
A Methodology for Rapid Optimization of HandelC Specifications
Author :
Libby, Joey C. ; Kent, Kenneth B.
Author_Institution :
Fac. of Comput. Sci., Univ. of New Brunswick, Fredericton, NB, Canada
fYear :
2009
fDate :
23-26 June 2009
Firstpage :
81
Lastpage :
87
Abstract :
Utilizing high level hardware description languages for the creation of customized circuits facilitates the rapid development and deployment of new hardware. While hardware design languages increase the speed at which hardware can be developed, creating hardware designs that are both efficient in resource usage and processing speed can be time consuming and require much experience. This problem is compounded more by the long design cycle times that are introduced by the long compilation and synthesis times that are required to translate a high level hardware description language to a circuit. This problem is addressed by performing some of the optimizations automatically, pre-synthesis, reducing the total number of synthesis cycles that are required, saving much development time.
Keywords :
formal specification; hardware description languages; software prototyping; HandelC specifications; design cycle times; high level hardware description languages; rapid optimization; synthesis cycles; Circuit synthesis; Communication system control; Computer science; Concurrent computing; Design optimization; Hardware design languages; Optimization methods; Parallel processing; Prototypes; Testing; Field Programmable Gate Array; HandelC; Hardware Design Flow; Rapid Prototyping;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Rapid System Prototyping, 2009. RSP '09. IEEE/IFIP International Symposium on
Conference_Location :
Paris
ISSN :
1074-6005
Print_ISBN :
978-0-7695-3690-3
Type :
conf
DOI :
10.1109/RSP.2009.31
Filename :
5158503
Link To Document :
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