Methodical Design Approaches to Radiation Effects Analysis and Mitigation in Flip-Flop Circuits

With transistor dimensions shrinking due to continued scaling, integrated circuits are increasingly susceptible to radiation upset. This paper presents a systematic methodology for evaluating circuit hardness, as well as graph clustering approaches to determine effective node separation to protect against upset due to multiple node charge collection. The methodology is circuit simulation based, making it efficient and usable by circuit designers. Example designs are presented to demonstrate the analysis and clustering for real flip-flop designs. Finally, the methodology is utilized to provide critical node separation for a new hardened flip-flop design that reduces the power and area by 27% and 19.5% respectively.