Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drain

Ultra deep submicron CMOS is a promising technology for wireless applications. In order to obtain an optimal RF performance, many trade-offs can be made during the development of a CMOS technology that is traditionally driven by digital requirements. Using logic devices from a 90 nm digital CMOS technology node, RF models are generated that allow feedback from RF designs and optimisation of the technology for RF applications. As a case study, the elevated source drain (/sup E/S/D) architecture is optimised for RF performance. The influence of this process optimisation on an extrinsic reliability threat is investigated using Electro-Static Discharge (ESD) withstanding capability.