A FPGA Based Real-time Design of Efficient Sifting Module in QKD System

Since the Quantum Key Distribution (QKD)technique makes it possible to construct an absolute secure cryptographic system by combing the One-time pad, QKD has drawn many attention these years. The insufficient implementation speed of the post-processing system of QKD is one of the greatest obstacle to wide application of QKD. The sifting module of QKD post-processing system needs to deal with the heaviest incoming load, it is of crucial importance to study how to design and implement an efficient sifting module to accelerate the QKD post-processing system. In this paper, an efficient FPGA based design scheme of the sifting module is presented. Our scheme can decrease the demands for storage resource and communication traffic obviously.