Electrical characteristics of single, double & surround gate vertical MOSFETs with reduced overlap capacitance

Author

Gili, E. ; Kunz, V.D. ; de Groot, C.H. ; Uchino, T. ; Donaghy, D. ; Hall, S. ; Ashburn, P.

Author_Institution

Dept. of Electron. & Comput. Sci., Southampton Univ., UK

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

533

Lastpage

536

Abstract

The vertical MOSFET structure is one of the solutions for reducing the channel length of devices under 50 nm. Surround gate structures can be realized which offer improved short channel effects and more channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented, which uses fillet local oxidation (FILOX) to reduce the overlap capacitance between the gate and the drain on the bottom of the pillar. Electrical characteristics of surround gate n-MOSFETs are presented and compared with results from single gate and double gate devices on the same wafer. The devices show good symmetry between the source on top and source on bottom configuration. The short channel effects of the surround gate MOSFETs are investigated.

Keywords

MOSFET; oxidation; 100 nm; 3 nm; FILOX process; channel length reduction; channel width; double gate MOSFET; fillet local oxidation; pillar bottom gate/drain capacitance; reduced overlap capacitance n-MOSFET; short channel effects; single gate MOSFET; surround gate MOSFET; top/bottom source symmetry; vertical MOSFET; Capacitance; Computer science; Dry etching; Electric variables; Electrodes; Fabrication; Lithography; MOSFET circuits; Oxidation; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7999-3

Type

conf

DOI

10.1109/ESSDERC.2003.1256931

Filename

1256931