Title :
Snapback circuit model for cascoded NMOS ESD over-voltage protection structures
Author :
Vassilev, V. ; Lorenzini, M. ; Jansen, Ph. ; Vashchenko, V. ; Yang, J.-J. ; Concannon, A. ; Archer, D. ; Groeseneken, G. ; Natarajan, M.I. ; Terbeek, M. ; Thijs, S. ; Choi, B.-J. ; Steyaert, M. ; Maes, H.E.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
This paper presents an equivalent circuit snapback model for the ESD domain operation of merged cascoded NMOS devices. The model reflects the specific breakdown operation of the structure at different gate bias conditions. An example for optimisation of the ESD behaviour of an output driver, utilising this protection device, is presented.
Keywords :
MOSFET; buffer circuits; circuit optimisation; driver circuits; electrostatic discharge; equivalent circuits; semiconductor device breakdown; semiconductor device models; ESD behaviour optimisation; ESD over-voltage protection structures; ESD structure snapback circuit model; I/O buffers; device breakdown operation; equivalent circuit; gate bias conditions; merged cascoded NMOS structures; output driver; Design optimization; Driver circuits; Electric breakdown; Electronic mail; Electrostatic discharge; Equivalent circuits; MOS devices; MOSFET circuits; Protection; Threshold voltage;
Conference_Titel :
European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7999-3
DOI :
10.1109/ESSDERC.2003.1256938
