Limiting Flexibility in Multiplication over GF(2m): A Design Methodology

Multiplication over the field GF(2^m) is computationally expensive, not least because the operation involves modulo reduction. It is typical to fix the field and field representation to improve performance, but some applications need to operate over multiple fields. This work investigates the cost of this flexibility with application to elliptic curve cryptography (ECC), both analytically and empirically through FPGA implementation. A design methodology is presented for limiting the flexibility to a number of prescribed fields with the representation fixed for each, and the methodology is applied to the design of a bit-serial multiplier over GF(2^m). FPGA implementation results are given; and it is shown that the practical advantage of the proposed approach is considerable in terms of speed versus area trade-off. In fact, only a 12.3% area overhead was incurred by the flexible implementation compared to the fixed field implementation, while still achieving the same speed performance