A 1-V 5.2-GHz 27.5-mW fully-integrated CMOS WLAN synthesizer

Author

Leung, Gerry C T ; Luong, Howard C.

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

113

Lastpage

116

Abstract

A 1-V 5.2-GHz CMOS frequency synthesizer for WLAN 802.11a transceivers is implemented in a 0.18-/spl mu/m standard CMOS technology. A novel design technique is proposed to achieve a 1-V 5.2-GHz low-power programmable frequency divider for the synthesizer. At a 1-V supply, the synthesizer measures a phase noise of -136 dBc/Hz at a 20-MHz frequency offset and a spurious tone of less than -80 dBc while dissipating 27.5 mW and occupying a total core area of 1.03 mm/sup 2/.

Keywords

CMOS integrated circuits; frequency synthesizers; phase noise; programmable circuits; transceivers; wireless LAN; 0.18 microns; 1 V; 20 MHz; 27.5 mW; 5.2 GHz; CMOS frequency synthesizer; WLAN 802.11a transceivers; WLAN synthesizer; design technique; fully-integrated CMOS; low-power programmable frequency divider; phase noise; standard CMOS technology; Area measurement; CMOS technology; Frequency conversion; Frequency measurement; Frequency synthesizers; Noise measurement; Phase measurement; Phase noise; Transceivers; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257085

Filename

1257085