Modelling impact of digital substrate noise on embedded regenerative comparators

Author

Zinzius, Yann ; Gielen, Georges ; Sansen, Willy

Author_Institution

K.U. Leuven, Belgium

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

253

Lastpage

256

Abstract

This paper presents an analysis and high-level modelling method used to estimate the impact of digital substrate noise on a CMOS regenerative comparator embedded in a mixed-signal environment. A test chip was designed in a 0.35 /spl mu/m heavily doped substrate technology in order to measure the impact of digital noise on embedded CMOS regenerative comparators. Secondly an efficient equation-based model of the impact of the digital substrate noise on embedded CMOS regenerative comparators was derived. It is based on the statistical analysis of the jitter measured at the output of the comparator.

Keywords

CMOS integrated circuits; comparators (circuits); embedded systems; high level synthesis; integrated circuit modelling; integrated circuit noise; noise measurement; statistical analysis; substrates; 0.35 microns; CMOS regenerative comparator; analysis method; digital noise; digital substrate noise; efficient equation-based model; embedded regenerative comparators; heavily doped substrate technology; high-level modelling method; jitter analysis; mixed-signal environment; modelling impact; statistical analysis; test chip; Clocks; Equations; Noise measurement; Noise reduction; Semiconductor device measurement; Semiconductor device modeling; Signal analysis; Switches; Topology; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257120

Filename

1257120