Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies

Leakage current is becoming an increasingly important fraction of the total power dissipation of integrated circuits. This work focuses on leakage power minimization in light of the growing significance of gate leakage current. The need to consider gate leakage while determining the sleep-state pattern is demonstrated. Circuit reorganization and sleep-state assignment techniques are presented for gate and total leakage minimization of static and dynamic circuits. We also re-evaluate the MTCMOS circuit scheme for total leakage minimization.