A 3.125-Gb/s CMOS word alignment demultiplexer for serial data communications

Author

Zhao, Wen-Hu ; Wang, Zhi-Gong ; Zhu, En

Author_Institution

Inst. of RF & OE ICs, Southeast Univ., Nanjing, China

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

389

Lastpage

392

Abstract

A cascaded 1:10 demultiplexer with comma detection and word alignment has been developed and fabricated using a 0.25/spl mu/m CMOS technology. It operates at half the clock frequency of the input data and uses a word alignment clock divider to ensure the parallel data output at the word boundary. Tested on wafer, the chip can operate from 1Gb/s to 3.125Gb/s to meet various specifications. The measured peak-peak voltage is above 700mV based on 50 /spl Omega/ load and the phase jitter are 11ps rms at the 3.125-Gb/s standard input bit rate. The power consumption is 234mW with a 3.3V supply and the chip area is 1.3mm/sup 2/.

Keywords

CMOS integrated circuits; cascade systems; clocks; data communication; demultiplexing equipment; 0.25 microns; 1 to 3.123 Gbit/s; 234 mW; 3.125 Gbit/s; 3.3 V; 50 ohms; 700 mV; CMOS technology; CMOS word alignment demultiplexer; cascaded demultiplexer; comma detection; half clock frequency; parallel data output; serial data communications; word alignment clock divider; word boundary; CMOS technology; Clocks; Data communication; Frequency conversion; Jitter; Measurement standards; Phase measurement; Semiconductor device measurement; Testing; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257154

Filename

1257154