Design of a hybrid controller ASIC for a VRM using 90 nm CMOS process

This paper proposes an ASIC implementation of the nonlinear controller in Voltage Regulator Modules (VRM) for high end microprocessors first proposed by [1] and demonstrated on discrete level by [2], [3]. The design scheme is presented where the driver is separated from the controller to enable its integration with the MOSFET using the Driver-MOS, (DrMOS) concept proposed by Intel [4]. The controller, designed using STpsilas 90 nm CMOS process, has increased speed and size performance and can be integrated into the I/O hub or Southbridge component PC chipsets which are similarly fabricated on sub-micrometer process. The transconductance of the process is however low giving rise to accuracy problems. We validated the design in simulations by comparing system and transistor level implementation in Saber and Cadence respectively. The nonlinear control scheme coupled with adaptive voltage positioning (AVP) enables high speed response to load transients at relatively constant output impedance. The design is realized in layout with Calibrepsilas verification tool running STpsilas design rule check (DRC) runset and is layout versus schematic clean (LVS).