DocumentCode :
2449162
Title :
An SRAM weak cell fault model and a DFT technique with a programmable detection threshold
Author :
Pavlov, Andrei ; Sachdev, Manoj ; De Gyvez, Jose Pineda
Author_Institution :
Waterloo Univ., Ont., Canada
fYear :
2004
fDate :
26-28 Oct. 2004
Firstpage :
1006
Lastpage :
1015
Abstract :
SRAM cell stability has become an important design and test issue owing to significant process spreads, non-ideal operational conditions, and subtle manufacturing defects in scaled-down geometries. In this article, we carry out an extensive SRAM SNM sensitivity analysis and propose an SRAM cell stability fault model for weak cell detection. This fault model is used to design and verify a proposed digitally programmable design-for-test (DFT) technique targeting the weak cell detection in embedded SRAMs (eSRAM).
Keywords :
SRAM chips; design for testability; fault diagnosis; integrated circuit design; integrated circuit modelling; integrated circuit testing; sensitivity analysis; SRAM cell stability fault model; design for testability; digitally programmable DFT technique; embedded SRAM; programmable detection threshold; sensitivity analysis; subtle manufacturing defects; weak cell detection; Design for testability; Fault detection; Geometry; Manufacturing processes; Random access memory; Robustness; Sensitivity analysis; Stability analysis; System-on-a-chip; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
Type :
conf
DOI :
10.1109/TEST.2004.1387366
Filename :
1387366
Link To Document :
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