Title :
Efficient hardware support for the Partitioned Global Address Space
Author :
Fröning, Holger ; Litz, Heiner
Author_Institution :
Comput. Archit. Group, Univ. of Heidelberg, Mannheim, Germany
Abstract :
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory. Remote memory access is possible by forwarding local load or store transactions to remote nodes. No software layers are involved in a remote access, neither on origin or target side: a user level process can directly access remote locations without any kind of software involvement. We have implemented the architecture as an FPGA-based prototype in order to demonstrate the functionality of the complete system. This prototype also allows real world measurements in order to show the performance potential of this architecture, in particular for fine grain memory accesses like they are typically used for synchronization tasks.
Keywords :
field programmable gate arrays; parallel architectures; shared memory systems; synchronisation; FPGA-based prototype; communication engine architecture; field programmable gate array; noncoherent distributed shared memory systems; partitioned global address space; remote memory access; synchronization tasks; user level process; Application software; Computer architecture; Distributed computing; Electronics packaging; Engines; Hardware; High performance computing; Message passing; Prototypes; Software prototyping; computer communications; distributed shared memory; high performance networking;
Conference_Titel :
Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
978-1-4244-6533-0
DOI :
10.1109/IPDPSW.2010.5470851
