FPGA implementation of a Digital Front End block for a Multi-Carrier Multi-Antenna system

Author

Mocanu, V. ; Anghel, C. ; Enescu, A.A.

Author_Institution

Telecommun. Dept., Politeh. Univ. of Bucharest, Bucharest, Romania

Volume

2

fYear

2009

fDate

12-14 Oct. 2009

Firstpage

431

Lastpage

434

Abstract

This paper describes a Field Programmable Gate Array (FPGA) implementation of a Digital Front End (DFE) block for a Multi-Carrier Multi-Antenna (MCMA) system. The decimation/ interpolation filters used for obtaining the required channel bandwidth are split into several low order decimation/ interpolation stages, each of them being implemented as a polyphase filter. At the receiver, the DFE contains also a frame synchronization block and an automatic gain controller (AGC). The targeted chips are members of Virtex 2 family, area and speed result being provided for each block.

Keywords

antenna arrays; automatic gain control; bandwidth allocation; field programmable gate arrays; filtering theory; interpolation; synchronisation; telecommunication control; wireless channels; AGC; DFE; FPGA implementation; MCMA system; Virtex 2 family; automatic gain controller; channel bandwidth; decimation/interpolation filter; digital front end block; field programmable gate array; frame synchronization block; multicarrier multiantenna system; polyphase filter; targeted chip; Antennas and propagation; Diversity reception; Field programmable gate arrays; Finite impulse response filter; Frequency; Interpolation; MIMO; OFDM modulation; Receiving antennas; Transmitting antennas;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference, 2009. CAS 2009. International

Conference_Location

Sinaia

ISSN

1545-827X

Print_ISBN

978-1-4244-4413-7

Type

conf

DOI

10.1109/SMICND.2009.5336686

Filename

5336686