7.3 Gb/s universal BCH encoder and decoder for SSD controllers

Author

Hoyoung Yoo ; Youngjoo Lee ; In-Cheol Park

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea

fYear

2014

fDate

20-23 Jan. 2014

Firstpage

37

Lastpage

38

Abstract

This paper presents a universal BCH encoder and decoder that can support multiple error-correction capabilities. A novel encoding architecture and on-demand syndrome calculation technique is proposed to reduce both hardware complexity and power consumption. Based on the proposed methods, 32-parallel universal encoder and decoder are designed for BCH (8192+14t, 8192, t) codes, where the error-correction capability t is configurable to 8, 11, 16, 24, 32, and 64. The prototype chip achieves a throughput of 7.3 Gb/s and occupies 2.24 mm² in 0.13μm CMOS technology.

Keywords

BCH codes; CMOS digital integrated circuits; error correction; flash memories; CMOS technology; SSD controllers; bit rate 7.3 Gbit/s; encoding architecture; hardware complexity reduction; multiple error-correction capabilities; on-demand syndrome calculation technique; power consumption reduction; size 0.13 mum; solid-state drives; universal BCH decoder; universal BCH encoder; Complexity theory; Computer architecture; Decoding; Flash memories; Hardware; Logic gates; Polynomials;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific

Conference_Location

Singapore

Type

conf

DOI

10.1109/ASPDAC.2014.6742862

Filename

6742862