DocumentCode
2453374
Title
Permutation admissibility in shuffle-exchange networks with arbitrary number of stages
Author
Das, Nabanita ; Bhattacharya, Bhargab B. ; Menon, Rekha ; Bezrukov, Sergei L.
Author_Institution
Indian Stat. Inst., Calcutta, India
fYear
1998
fDate
17-20 Dec 1998
Firstpage
270
Lastpage
276
Abstract
The set of input-output permutations that are routable through a multistage interconnection network without any conflict (known as the admissible set), plays an important role in determining the capability of the network. Recent works on the permutation admissibility problem of shuffle-exchange networks (SEN) of size N×N, deal with (n+k) stages, where n=log2N, and k denotes the number of extra stages. For k=0 or 1, O(Nn) algorithms exist to check if any permutation is admissible, but for k⩾2, a polynomial time solution is not yet known. The more general problem of finding the minimum number (m) of shuffle-exchange stages required to realize an arbitrary permutation, 1⩽m⩽2n-1, is also an open problem. In this paper, we present an O(Nn) algorithm that checks whether a given permutation P is admissible in an m stage SEN, 1⩽m⩽n, and determines in O(Nnlogn) time the minimum number of stages m of shuffle-exchange, required to realize P. Thus, a single-stage shuffle-exchange network will be able to realize such a permutation with m passes, by recirculating all the paths m times through a single-stage, i.e., with minimum transmission delay, which, otherwise cannot be achieved with a fixed-stage SEN. Furthermore, we present a necessary condition for permutation admissibility in an m stage SEN, where n<m⩽2n-1
Keywords
hypercube networks; multistage interconnection networks; network routing; parallel architectures; admissible set; input-output permutations; minimum transmission delay; multistage interconnection network; permutation admissibility; polynomial time solution; shuffle-exchange networks; single-stage network; Intelligent networks; Multiprocessor interconnection networks;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing, 1998. HIPC '98. 5th International Conference On
Conference_Location
Madras
Print_ISBN
0-8186-9194-8
Type
conf
DOI
10.1109/HIPC.1998.737998
Filename
737998
Link To Document