• DocumentCode
    245350
  • Title

    SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs

  • Author

    Ambrose, Jude Angelo ; Peddersen, Jorgen ; Parameswaran, Sri ; Labios, Alvin ; Yachide, Yusuke

  • Author_Institution
    Sch. of Comput. Sci. & Eng., Univ. of New South Wales Sydney, Sydney, NSW, Australia
  • fYear
    2014
  • fDate
    20-23 Jan. 2014
  • Firstpage
    267
  • Lastpage
    273
  • Abstract
    The Multiprocessor System-on-Chip (MPSoC) paradigm as a viable implementation platform for parallel processing has expanded to encompass embedded devices. The ability to execute code in parallel gives MPSoCs the potential to achieve high performance with low power consumption. In order for sequential legacy code to take advantage of the MPSoC design paradigm, it must first be partitioned into data flow graphs (such as Kahn Process Networks - KPNs) to ensure the data elements can be correctly passed between the separate processing elements that operate on them. Existing techniques are inadequate for use in complex legacy code. This paper proposes SDG2KPN, a System Dependency Graph to KPN conversion methodology targeting the conversion of legacy code. By creating KPNs at the granularity of the function-/procedure-level, SDG2KPN is the first of its kind to support shared and global variables as well as many more program patterns/application types. We also provide a design flow which allows the creation of MPSoC systems utilizing the produced KPNs. We demonstrate the applicability of our approach by retargeting several sequential applications to the Tensilica MPSoC framework. Our system parallelized AES, an application of 950 lines, in 4.8 seconds, while H.264, of 57896 lines, took 164.9 seconds to parallelize.
  • Keywords
    data flow graphs; low-power electronics; multiprocessing systems; parallel processing; system-on-chip; H.264; Kahn process networks; MPSoC design paradigm; SDG2KPN; Tensilica MPSoC framework; data flow graphs; embedded devices; function-level KPN generation; function-procedure-level; low power consumption; multiprocessor system-on-chip paradigm; parallel processing; sequential legacy code; system dependency graph to KPN conversion methodology; time 164.9 s; time 4.8 s; Australia; Generators; Input variables; Manuals; Parallel processing; Program processors; Syntactics;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific
  • Conference_Location
    Singapore
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2014.6742901
  • Filename
    6742901