Resiliency for many-core system on a chip

Author

Karnik, T. ; Tschanz, James ; Borkar, N. ; Howard, John ; Vangal, Sriram ; De, Vivek ; Borkar, Shekhar

Author_Institution

Intel Corp. Hillsboro, Hillsboro, OR, USA

fYear

2014

fDate

20-23 Jan. 2014

Firstpage

388

Lastpage

389

Abstract

Resilient techniques are commonly employed for dynamic and static variation tolerance. In this paper, we present an adaptive clocking technique that achieves 31% throughput increase with 15% energy reduction, and an adaptive interconnect fabric technique that increases bandwidth by 63% with 14.6% energy reduction. We also discuss variations in many-core microprocessors and some techniques to enable a resilient many-core system on a chip.

Keywords

clocks; integrated circuit interconnections; microprocessor chips; system-on-chip; adaptive clocking; adaptive interconnect fabric technique; dynamic variation tolerance; many-core microprocessors; many-core system-on-a-chip; resilient techniques; static variation tolerance; Bandwidth; Clocks; Delays; Fabrics; Integrated circuit interconnections; Microprocessors; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific

Conference_Location

Singapore

Type

conf

DOI

10.1109/ASPDAC.2014.6742921

Filename

6742921

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=245409