• DocumentCode
    24569
  • Title

    Dual-Level Adaptive Supply Voltage System for Variation Resilience

  • Author

    Kyu-Nam Shim ; Jiang Hu ; Silva-Martinez, Jose

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA
  • Volume
    21
  • Issue
    6
  • fYear
    2013
  • fDate
    Jun-13
  • Firstpage
    1041
  • Lastpage
    1052
  • Abstract
    VLSI circuits of the 45-nm technology and beyond are increasingly affected by process variations as well as aging effects. Overcoming the variations inevitably requires additional power expense, which in turn aggravates the power and heat problem. Adaptive supply voltage (ASV) is an arguably power-efficient approach for variation resilience since it attempts to allocate power resources only to where the negative effect of variations is strong. We propose a dual-level ASV (dual-ASV) system for designs containing many timing critical paths. This system can simultaneously provide ASV at both coarse-grained and fine-grained levels, and has limited power routing overhead. The dual-ASV system is compared with conventional ASV through SPICE simulations on benchmark circuits. The results indicate that the dual-ASV system consumes significantly less power and achieves similar performance in the presence of variations.
  • Keywords
    SPICE; VLSI; power integrated circuits; power supply circuits; SPICE simulations; VLSI circuits; dual-level ASV; dual-level adaptive supply voltage system; power resources; variation resilience; Aging; Logic gates; Regulators; Switches; Timing; Transistors; Voltage control; Adaptive system; VLSI; aging; process variation; resilience;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2012.2203326
  • Filename
    6238381