DocumentCode
2458019
Title
Substrate parasitic extraction for RF integrated circuits
Author
Cathelin, Andreia ; Leclercq, Youri ; Saias, Daniel ; Belot, Didier ; Clément, Francois J R
Author_Institution
STMicroelectonics, Crolles, France
fYear
2002
fDate
2002
Firstpage
1107
Abstract
Summary form only given. Accurately predicting the impact of substrate parasitics in Radio Frequency (RF) design with simulations is one of the major concerns to ensure first silicon success in a System on Chip (SoC) approach. The practical design experience of a 2 GHz RF front-end circuit (designed in a 0.35 μm SiGe BiCMOS technology), presented here, illustrates how measurements results can be accurately predicted using a substrate parasitic extractor
Keywords
BiCMOS integrated circuits; UHF integrated circuits; integrated circuit design; integrated circuit modelling; substrates; 0.35 micron; 2 GHz; RF design; RF integrated circuits; RFICs; SiGe BiCMOS technology; design flow; radio frequency design; substrate coupling issues; substrate parasitic extraction; substrate parasitic modelling; Automatic testing; Circuit simulation; Design automation; Europe; Frequency measurement; RF signals; Radio frequency; Radiofrequency integrated circuits; Signal design;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location
Paris
ISSN
1530-1591
Print_ISBN
0-7695-1471-5
Type
conf
DOI
10.1109/DATE.2002.998463
Filename
998463
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