DocumentCode
2458771
Title
Energy efficient addition by two-sided carry-reverse computation
Author
Wimer, Shmuel ; Stanislavsky, Amnon ; Kolodny, Avinoam
Author_Institution
EE Dept., Technion - Israel Inst. of Technol., Haifa, Israel
fYear
2012
fDate
14-17 Nov. 2012
Firstpage
1
Lastpage
3
Abstract
This paper shows how addition can be accelerated by considering the carry as being propagating from LSB and from MSB towards a midpoint. A closed form expression for the optimal midpoint is derived. The acceleration is used to reduce the energy consumed by the adder. A 64 bit adder targeting 500MHz clock frequency, designed in 65 nanometers, consumed 18% less energy and area compared to adder generated by state-of-the-art EDA synthesis tool.
Keywords
VLSI; adders; carry logic; logic design; LSB; MSB; energy consumption reduction; energy efficient addition; frequency 500 MHz; least significant bit; most significant bits; size 65 nm; state-of-the-art EDA synthesis tool; storage capacity 64 bit; two-sided carry-reverse computation; Acceleration; Adders; Clocks; Delay; Energy efficiency; Repeaters; Very large scale integration; Adders; Low-energy; VLSI design;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical & Electronics Engineers in Israel (IEEEI), 2012 IEEE 27th Convention of
Conference_Location
Eilat
Print_ISBN
978-1-4673-4682-5
Type
conf
DOI
10.1109/EEEI.2012.6377135
Filename
6377135
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