Teaching computer architecture/organisation using simulators

Experience shows that many students, especially those with little hardware background, encounter difficulties in understanding the consequences and even concepts of conventional instruction pipelining; superscalar instruction processing is even more complicated and harder to understand. It is particularly difficult to statically teach the concept of a pipeline. Therefore we developed software to simulate and dynamically visualize the processing of instructions by pipelined (superscalar) processors. Three simulators have been developed: WinDLX is based on Hennessy/Pattersons DLX architecture and is modeled at the architecture level, therefore very little processor-internal information is given. MIPSim is based on Patterson/Hennessy´s MIPS processor book and is modeled at the computer organization level, functional units like register file, pipeline registers, multiplexers are visible and MIPSim displays content and dynamic behavior of such units. M10kSim is based on the MIPS R10000 architecture and models the instruction decode and dispatch unit, the branch unit, the instruction queues and the functional units. Concepts like register renaming, branch history table, branch resume buffer, out of order execution can be explained easily using the simulator. Teaching cache organization is an easier task, nevertheless visualising cache activities helps understanding the dynamics of a cache memory, Xcache is a simulator which displays the interactions between instruction memory and instruction cache, data memory and data cache, respectively.