Optimized BF3 P2 LAD implantation with Si-PAI for shallow, abrupt and high quality p+/n junctions formed using low temperature SPE annealing

Shallow junction formation by low temperature SPE (solid phase epitaxial growth) is an attractive activation technique, as it can be easily integrated into disposable spacer or high-k gate process schemes for sub-100nm technology nodes. In this paper we report our experimental results using BF₃ P²LAD implantation at wafer biases between 600V and 5kV and low temperature SPE annealing in the 550-650°C range to achieve shallow and abrupt p⁺/n junctions. Using various Si-PAI (pre-amorphizing implantation) conditions between 5keV and 30keV, we were able to optimize the location of the PAI residual implant damage relative to the electrical junction depth to achieve acceptable junction leakage values. Using specially prepared samples with simulated pMOS dopant profiles, p⁺/n junction leakage current as a function of the difference between the junction depth and the location of the PAI damage (X_j - EOR) could be determined. The X_j - EOR values were also verified by SIMS and cross-sectional X-TEM micrographs.