Receiver Architectures and Design Tradeoffs for CDMA Interference Cancellation

This paper investigates the design of commercially viable CDMA basestation receivers that incorporate interference cancellation. Results are given for cdma2000 1xEV-DO but also apply to WCDMA HSUPA. The effect of receiver memory size is determined for canceling packets transmitted with hybrid-ARQ. Performance-complexity tradeoffs are presented for implementing iterative and successive interference cancellation of asynchronous user transmissions. Multipath channel estimation techniques of varying complexity are compared based on sector throughput. Practical interference cancellation designs with moderate complexity are shown to achieve a large fraction of the gains of more elaborate techniques.