Segmented Digital Clock Manager- FPGA based Digital Pulse Width Modulator Technique

A new digital pulse width modulator (DPWM) design for a field programmable gate array (FPGA) based systems is presented in this paper. The proposed architecture fully utilizes the digital clock manager (DCM) resources available on new FPGA boards. The proposed segmented DCM DPWM is a digital modulator architecture with low power that allows for high switching frequency operation. It relies on the power-optimized resources already existing on new FPGAs. The inherit phase shifting properties of the DCM blocks simplify the duty cycle generation. The architecture can be applied to achieve various number of bits for the DPWM resolution, and is implemented and verified experimentally on a Virtex4 FPGA board.