A low power high speed ROIC design for 1024×1024 IRFPA with novel readout stage

Author

Liu, Chang ; Lu, Wengao ; Chen, Zhongjian ; Bian, Haimei ; Ji, Lijiu

Author_Institution

Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Beijing

fYear

2008

fDate

8-10 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10 M/s per channel, with the total power dissipation of 56 mW.

Keywords

CMOS image sensors; focal planes; high-speed integrated circuits; integrated circuit design; low-power electronics; readout electronics; IRFPA; image system; low power high speed ROIC design; power management; read-out integrated circuit; short-wave infrared focal plane array; total power dissipation; CMOS logic circuits; Capacitors; Cooling; Detectors; Logic arrays; Logic devices; Power amplifiers; Power dissipation; Prototypes; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-2539-6

Electronic_ISBN

978-1-4244-2540-2

Type

conf

DOI

10.1109/EDSSC.2008.4760710

Filename

4760710