A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array

Author

Kim, Hoonki ; Min, Young Jae ; Kim, Yongh Wan ; Kim, Soowon

Author_Institution

Dept. of Electron. Eng., Korea Univ., Seoul

fYear

2008

fDate

8-10 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

A 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for biomedical applications is presented. The proposed SAR ADC achieves rail-to-rail input range and low power consumption. A Digital-to-Analog Converter (DAC) using C-2C capacitor array and dynamic comparator is used for low power consumption. It is realized in 0.18 mum standard CMOS technology. This ADC has signal to noise and distortion ratios (SNDR) of 53.8dB for 1.5 V supply voltage. It consumes 13.4 muW at sampling rates of 137 kS/s.

Keywords

CMOS integrated circuits; analogue-digital conversion; capacitors; digital-analogue conversion; low-power electronics; ADC; C-2C capacitor array; CMOS technology; SAR; biomedical applications; digital-to-analog converter; dynamic comparator; low power consumption; noise figure 53.8 dB; power 13.4 muW; signal to noise and distortion ratios; size 0.18 mum; successive approximation register; voltage 1.5 V; Analog-digital conversion; CMOS technology; Capacitors; Digital-analog conversion; Distortion; Energy consumption; Rail to rail inputs; Sampling methods; Signal to noise ratio; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-2539-6

Electronic_ISBN

978-1-4244-2540-2

Type

conf

DOI

10.1109/EDSSC.2008.4760721

Filename

4760721