DocumentCode :
2467411
Title :
FPGA Implementation of Evolvable Block-based Neural Networks
Author :
Merchant, Saumil ; Peterson, Gregory D. ; Park, Sang Ki ; Kong, Seong G.
Author_Institution :
Univ. of Tennessee, Knoxville
fYear :
0
fDate :
0-0 0
Firstpage :
3129
Lastpage :
3136
Abstract :
This paper presents a hardware implementation approach for block-based neural networks (BbNNs) on a Programmable System-On-Chip. This is an intrinsic online evolution system that can be genetically evolved and adapted to changes in input data patterns dynamically without any need for multiple FPGA reconfigurations to accommodate various network structure/parameter changes. This removes a considerable bottleneck for performance. The research presented here is a first step towards an evolvable system that can be implemented as an embedded system.
Keywords :
embedded systems; field programmable gate arrays; genetic algorithms; neural chips; system-on-chip; FPGA implementation; block-based neural networks; embedded system; evolvable BbNN; intrinsic online evolution system; programmable system-on-chip; Application specific integrated circuits; Artificial neural networks; Costs; Electronic mail; Evolutionary computation; Field programmable gate arrays; Genetic algorithms; Neural network hardware; Neural networks; Neurons;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Evolutionary Computation, 2006. CEC 2006. IEEE Congress on
Conference_Location :
Vancouver, BC
Print_ISBN :
0-7803-9487-9
Type :
conf
DOI :
10.1109/CEC.2006.1688705
Filename :
1688705
Link To Document :
بازگشت