Title :
Circuit/architecture for low-power high-performance 32-bit adder
Author :
Abu-Khater, I.S. ; Bellaouar, A. ; Elmasry, M.I. ; Yan, R.H.
Author_Institution :
VLSI Res. Group, Waterloo Univ., Ont., Canada
Abstract :
A novel 32-bit adder has been designed using a Conditional Sum Adder (CSA) architecture and CPL-like logic implementation. The new implementation outperforms several architectures such as CLA, CS and Manchester which use the CMOS circuit styles (CPL, DPL, TG, static-conventional) in terms of power and speed. This is verified for a range of power supply voltage from 3.3 V down to 1 V. The comparison is carried out for two designs, minimum size and optimized speed
Keywords :
CMOS logic circuits; adders; circuit optimisation; integrated circuit design; logic design; 1 to 3.3 V; 32 bit; CMOS; CPL-like logic implementation; adder; conditional sum architecture; minimum size; optimized speed; power supply voltage; Adders; Circuits; Computer architecture; Power dissipation;
Conference_Titel :
VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on
Conference_Location :
Buffalo, NY
Print_ISBN :
0-8186-7035-5
DOI :
10.1109/GLSV.1995.516028
