DocumentCode :
2471288
Title :
MARS-C: modeling and reduction of soft errors in combinational circuits
Author :
Miskov-Zivanov, Natasa ; Marculescu, Diana
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
fYear :
0
fDate :
0-0 0
Firstpage :
767
Lastpage :
772
Abstract :
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we present a symbolic framework based on BDDs and ADDs that enables analysis of combinational circuit reliability from different aspects: output susceptibility to error, influence of individual gates on individual outputs and overall circuit reliability, and the dependence of circuit reliability on glitch duration, amplitude, and input patterns. This is demonstrated by the set of experimental results, which show that the mean output error susceptibility can vary from less than 0.1%, for large circuits and small glitches, to about 30% for very small circuits and large enough glitches. The results obtained with the proposed symbolic framework are within 7% average error and up to 5000times speedup when compared to HSPICE detailed circuit simulation. The framework can be used for selective gate sizing targeting radiation hardening which is done only for gates with error impact exceeding a certain threshold. Using such a technique, soft error rate (SER) can be reduced by 25-67% for various threshold values, when applied to a subset of ISCAS´85 and mcnc ´91 benchmarks
Keywords :
Boolean functions; binary decision diagrams; circuit reliability; combinational circuits; logic design; radiation hardening (electronics); ADD; BDD; HSPICE; circuit analysis; circuit reliability; circuit simulation; combinational circuits; feature size shrinking; nanoscale circuits; radiation effect; radiation hardening; selective gate sizing; soft errors modeling; soft errors reduction; supply voltages reduction; transient faults; Boolean functions; Circuit analysis; Circuit faults; Circuit simulation; Combinational circuits; Data structures; Error analysis; Pattern analysis; Radiation hardening; Voltage; Reliability; SER; reliability symbolic techniques;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location :
San Francisco, CA
ISSN :
0738-100X
Print_ISBN :
1-59593-381-6
Type :
conf
DOI :
10.1109/DAC.2006.229323
Filename :
1688899
Link To Document :
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