DocumentCode :
2471573
Title :
Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems
Author :
Leung, Lap-Fai ; Tsui, Chi-ying
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol.
fYear :
0
fDate :
0-0 0
Firstpage :
833
Lastpage :
838
Abstract :
With the advent of the multiple IP-core based design using network on chip (NoC), it is possible to run multiple applications concurrently. For applications with hard deadline, guaranteed services (GS) are required to satisfy the deadline requirement. GS typically under-utilizes the network resources. To increase the resources utilization efficiency, GS applications are always complement with the best-effort services (BE). To allow more resource available for BE, the resource reservation for GS applications, which depends heavily on the scheduling of the computation and communication, needs to be optimized. In this paper we propose a new approach based on optimal link scheduling to judiciously schedule the packets on each of the links such that the maximum latency of the GS application is minimized with minimum network resources utilization. To further increase the performance, we propose a router architecture using a shared-buffer implementation scheme. The approach is formulated using integer linear programming (ILP). We applied our algorithm on real applications and experimental results show that significant improvement on the overall execution time and link utilization can be achieved
Keywords :
integer programming; integrated circuit design; linear programming; microprocessor chips; network routing; network-on-chip; processor scheduling; resource allocation; guaranteed services performance; integer linear programming; multiple IP core; network on chip; network resource utilization; network-on-chip systems; optimal link scheduling; resource reservation; router architecture; shared buffer scheme; Application software; Computer architecture; Delay; Design engineering; Intelligent networks; Network-on-a-chip; Processor scheduling; Resource management; Tiles; Wire; Algorithms; Design; Latency; Network-on-Chip; Performance; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2006 43rd ACM/IEEE
Conference_Location :
San Francisco, CA
ISSN :
0738-100X
Print_ISBN :
1-59593-381-6
Type :
conf
DOI :
10.1109/DAC.2006.229271
Filename :
1688912
Link To Document :
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